Over the past generation, integrated circuits have grown in complexity to accommodate the ever demanding thirst for higher power and greater performance. With the increasing complexity of integrated circuits (ICs), there has been a tremendous push to improve reliability of the finished product. Great progress has been made in all phases of fabrication to provide reliable finished products. Reliability of integrated circuits is of paramount importance as it affects the overall quality of the finished product and, ultimately, the return on investment.
Failure analysis has become a critical requirement during a new product design. Failure analysis includes applying a selected voltage through a circuit input and observing the circuit output voltage by using probes. The probes are connected to the contacts of the underlying circuits and the input and output voltages at the circuits are measured through the probes. Due to the sheer volume of contacts and due to space limitations at the surface of the IC device, the number of probes that may be practically connected to the contacts is limited thereby reducing the number of circuits that may be probed. Additionally, the package configuration, such as a flip chip package, of the IC device makes applying these probes and examining the input and output voltages through these probes extremely difficult.
Further, conventional probes provide contact level characterization rather than cell level characterization. As a result, when a failure occurs during a test, the traditional probe identifies the location of the failure at a transistor level. In order to determine which of the underlying circuits caused a failure, the IC device has to be planarized to the transistor level and each transistor tested for integrity. As the number of transistors can be extremely large, this type of failure analysis testing is both time consuming and costly.
It would be advantageous to have a scheme that will provide a cell level characterization rather than contact level characterization of the IC device. It would also be advantageous if the scheme works for all types of package configuration. It would also be advantageous to have a scheme that addresses the spatial limitation at the surface of the IC device for placing the probe so that the number of circuits that can be tested is not limited by the spatial limitation at the top surface of the IC device.